Intel 9 Series Chipset Power Up Timing and Signal Interpretation.

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[size=17.3333px]Intel 9 Series Chipset Power Up Timing and Signal Interpretation.

• One, does not support deep sleep, from G3 / S5 to S3 / S0 state
  

[size=17.3333px]Timing diagram:

                               
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• Second, the signal explained: VCCRTC: RTC circuit power supply bridge to save the CMOS parameters.
  

• RTCRST #: RTC reset signal of the bridge circuit, 3V or more high, compared to 6 \ 7 series. 32.768KHz: 32.768KHz crystal next to the bridge, the bridge to the crystal power supply, crystal frequency to the bridge.
  

• VCCDSW3_3: deep sleep standby voltage bridge (Deep Sleep Well), 3.3V. When deep sleep is not supported, this voltage is connected to VCCSUS3_3 together.
  

• DPWROK: Bridge of good deep sleep standby voltage, the voltage is 3.3V. This signal is associated with RSMRST # when deep sleep is not supported.
  

• SLP_SUS #: deep sleep state indication signal emitted bridge, may be used to control the light sleep standby voltage (eg VCCSUS) opening and closing.
  

• Does not support depth Sleep, SLP_SUS # is floating.
  

• VCCSUS3_3: light sleep standby power supply bridge, 3.3V.
  

• RSMRST #: shallow sleep standby voltage of the bridge is good, 3.3V.
  

• SUSCLK: 32.768KHz clock bridge issued, but not occupied motherboard.
  

• PWRBTN #: falling bridge receives a trigger signal, 3.3V-0V-3.3V, notification bridge can exit the sleep state.
  

• SLP_S5 #: rear axle receive PWRBTN #, set high SLP_S5 # to 3.3V, that out off.
  

• SLP_S4 #: Bridge set high SLP_S4 # to 3.3V, indicate out of hibernation.
  

• SLP_S3 #: SLP_S3 # Bridge set high as 3.3V, indicates the standby state and enters the power-on state S0.
  

• SLP_A #: active sleep Circuit (Active Sleep Well, referred to as ASW) emitted power bridges on signal for turning on the power supply module ME If the medium supports AMT and turn on the AMT function, this signal will be generated before the trigger; Turn off the AMT function, the signal timing and SLP_S3 # consistent. If the principle does not support AMT, SLP_A # is not used.
  

• SLP_LAN #: LAN subsystem sleep control, power control card. If the circuit does not use INTEL's integrated network card, this signal is not used. If used INTEL integrated network card to support the network wake up, this signal is high when the standby, Does not support the network wake up, this signal follows SLP_A # or SLP_S3 #.
  

• VCCASW: active sleep power supply circuit (ME module), controlled by SLP_A #. When SLP_A # is floating (AMT is not supported), VCCASW is used directly S0 state power supply, such as 1.05V bus power supply.
  

• VDIMM: refers to the memory power supply, commonly controlled by SLP_S4 # VCC: supply means S0 bridge voltage VCCCORE, VCC3_3, V5REF, bus-powered, VCCSA, VCCPLL the like, controlled SLP_S3 #.
  

• APWROK: active sleep good power circuit, when the support AMT, APWROK AMT controlled by a voltage; does not support AMT, APWROK and PWROK sync.
  

• PWROK: Board issued 3.3V high bridge voltage indicates the state S0 are OK.
  

• DRAMPWROK: PG to the CPU of the rear axle receive PWROK, notify the CPU, memory, power supply module OK.
  

• 25MHz Crystal Osc: 9 series chipset without clock chip, PCH bridge internal integrated clock module, starting from the 6 series, the bridge to increase 25M crystal, to the bridge The internal clock module provides the reference frequency.
  

• PCH Output Clocks: bridge output clock of each group.
  

• PROCPWRGD: rear axle normal read BIOS, to the CPU core voltage of the non-PG, the CPU indicates OK.
  

• SVID: When the CPU receives PROCPWRGD, CPU SVID sent to the CPU power chip, the DATA and CLK consisting of a standard serial bus and A pop-up ALERT # signal. Used to control the CPU core voltage.
  

• VccCore_CPU: CPU core power supply of the CPU chip output.
  

• SYS_PWROK: 3.3V issued by the high power chip CPU of the bridge, denotes a CPU core power supply OK.
  

• SUS_STAT #: This signal indicates that the system will soon enter a low power state.
  

[size=17.3333px]PLT_RST #: Bridge platform emitted reset 3.3V, resetting each device to the motherboard, the converted as a CPU reset.

会员600027

太高深了，全是英文的，看不懂呀。

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