强烈建议总结专业术语的代名词（方便新人）

会员14025

很多名词都看不懂啊 希望版主总结一下一个专业术语的代名词 方便新人一个看得懂高手的文章。

学不学得会看自己 但是看不懂很多的代名词也很头痛的

会员11289

请查阅Hardware book该书概括了几乎所有的电脑硬体和硬体专业术语，描述非常详尽，对维修人员非常有用，比如他在描述PCI接口时是这样描述的：
PCI (Technical)

This section is currently based solely on the work by Mark Sokos.
This file is not intended to be a thorough coverage of the PCI standard. It is for informational purposes only, and is intended to give designers and hobbyists an overview of the bus so that they might be able to design their own PCI cards. Thus, I/O operations are explained in the most detail, while memory operations, which will usually not be dealt with by an I/O card, are only briefly explained. Hobbyists are also warned that, due to the higher clock speeds involved, PCI cards are more difficult to design than ISA cards or cards for other slower busses. Many companies are now making PCI prototyping cards, and, for those fortunate enough to have access to FPGA programmers, companies like Xilinx are offering PCI compliant designs which you can use as a starting point for your own projects.

For a copy of the full PCI standard, contact:
PCI Special Interest Group (SIG)
PO Box 14070
Portland, OR 97214
1-800-433-5177
1-503-797-4207

Signal Descriptions:

AD(x)

Address/Data Lines.

CLK

Clock. 33 MHz maximum.

C/BE(x)

Command, Byte Enable.

FRAME

Used to indicate whether the cycle is an address phase or a data phase.

DEVSEL

Device Select.

IDSEL

Initialization Device Select

INT(x)

Interrupt

IRDY

Initiator Ready

LOCK

Used to manage resource locks on the PCI bus.

REQ

Request. Requests a PCI transfer.

GNT

Grant. indicates that permission to use PCI is granted.

PAR

Parity. Used for AD0-31 and C/BE0-3.

PERR

Parity Error.

RST

Reset.

SBO

Snoop Backoff.

SDONE

Snoop Done.

SERR

System Error. Indicates an address parity error for special cycles or a system error.

STOP

Asserted by Target. Requests the master to stop the current transfer cycle.

TCK

Test Clock

TDI

Test Data Input

TDO

Test Data Output

TMS

Test Mode Select

TRDY

Target Ready

TRST

Test Logic Reset
The PCI bus treats all transfers as a burst operation. Each cycle begins with an address phase followed by one or more data phases. Data phases may repeat indefinitely, but are limited by a timer that defines the maximum amount of time that the PCI device may control the bus. This timer is set by the CPU as part of the configuration space. Each device has its own timer (see the Latency Timer in the configuration space).
The same lines are used for address and data. The command lines are also used for byte enable lines. This is done to reduce the overall number of pins on the PCI connector.

The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address phase.

C/BE        Command Type
0000        Interrupt Acknowledge
0001        Special Cycle
0010        I/O Read
0011        I/O Write
0100        reserved
0101        reserved
0110        Memory Read
0111        Memory Write
1000        reserved
1001        reserved
1010        Configuration Read
1011        Configuration Write
1100        Multiple Memory Read
1101        Dual Address Cycle
1110        Memory-Read Line
1111        Memory Write and Invalidate
The three basic types of transfers are I/O, Memory, and Configuration.

PCI timing diagrams:

            ___     ___     ___     ___     ___     ___
CLK     ___|   |___|   |___|   |___|   |___|   |___|   |___

        _______                                   _________
FRAME          |_________________________________|

                ______  _______  ______  ______  ______
AD      -------<______><_______><______><______><______>---
                Address  Data1    Data2   Data3   Data4

                ______  _______________________________
C/BE    -------<______><_______________________________>---
                Command   Byte Enable Signals

         ____________                                   ___
IRDY                 |_________________________________|

         _____________                                  ___
TRDY                  |________________________________|

         ______________                                 ___
DEVSEL                 |_______________________________|


PCI transfer cycle, 4 data phases, no wait states. Data is transferred on the rising edge of CLK.

                         [1]              [2]        [3]
            ___     ___     ___     ___     ___     ___     ___     ___
CLK     ___|   |___|   |___|   |___|   |___|   |___|   |___|   |___|   |__

        _______                                                  _________
FRAME          |________________________________________________|

                                   A               B               C
                ______           ______________  ______  _____________
AD      -------<______>---------<______________><______><_____________>---
                Address           Data1           Data2   Data3

                ______  ______________________________________________
C/BE    -------<______><______________________________________________>---
                Command   Byte Enable Signals

                                                         Wait
         ____________                                    _____         ___
IRDY                 |__________________________________|     |_______|

                        Wait            Wait
         ______________________         ______                         ___
TRDY                           |_______|      |_______________________|

         ______________                                                ___
DEVSEL                 |______________________________________________|


PCI transfer cycle, with wait states. Data is transferred on the rising edge of CLK at points labelled A, B, and C.

Bus Cycles:

Interrupt Acknowledge (0000)

The interrupt controller automatically recognizes and reacts to the INTA (interrupt acknowledge) command. In the data phase, it transfers the interrupt vector to the AD lines.

Special Cycle (0001)

AD15-AD0        Description
0x0000        Processor Shutdown
0x0001        Processor Halt
0x0002        x86 Specific Code
0x0003 to 0xFFFF        Reserved
I/O Read (0010) and I/O Write (0011)

Input/Output device read or write operation. The AD lines contain a byte address (AD0 and AD1 must be decoded). PCI I/O ports may be 8 or 16 bits. PCI allows 32 bits of address space. On IBM compatible machines, the Intel CPU is limited to 16 bits of I/O space, which is further limited by some ISA cards that may also be installed in the machine (many ISA cards only decode the lower 10 bits of address space, and thus mirror themselves throughout the 16 bit I/O space). This limit assumes that the machine supports ISA or EISA slots in addition to PCI slots.

The PCI configuration space may also be accessed through I/O ports 0x0CF8 (Address) and 0x0CFC (Data). The address port must be written first.

Memory Read (0110) and Memory Write (0111)

A read or write to the system memory space. The AD lines contain a doubleword address. AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate which bytes are valid.

Configuration Read (1010) and Configuration Write (1011)

A read or write to the PCI device configuration space, which is 256 bytes in length. It is accessed in doubleword units. AD0 and AD1 contain 0, AD2-7 contain the doubleword address, AD8-10 are used for selecting the addressed unit a the malfunction unit, and the remaining AD lines are not used.

Address     Bit 32      16   15           0

00          Unit ID        | Manufacturer ID
04          Status         | Command
08          Class Code               | Revision
0C          BIST  | Header | Latency | CLS
10-24            Base Address Register
28          Reserved
2C          Reserved
30          Expansion ROM Base Address
34          Reserved
38          Reserved
3C          MaxLat|MnGNT   | INT-pin | INT-line
40-FF       available for PCI unit


Multiple Memory Read (1100)

This is an extension of the memory read bus cycle. It is used to read large blocks of memory without caching, which is beneficial for long sequential memory accesses.

Dual Address Cycle (1101)

Two address cycles are necessary when a 64 bit address is used, but only a 32 bit physical address exists. The least significant portion of the address is placed on the AD lines first, followed by the most significant 32 bits. The second address cycle also contains the command for the type of transfer (I/O, Memory, etc). The PCI bus supports a 64 bit I/O address space, although this is not available on Intel based PCs due to limitations of the CPU.

Memory-Read Line (1110)

This cycle is used to read in more than two 32 bit data blocks, typically up to the end of a cache line. It is more efficient than normal memory read bursts for a long series of sequential memory accesses.

Memory Write and Invalidate (1111)

This indicates that a minimum of one cache line is to be transferred. This allows main memory to be updated, saving a cache write-back cycle.

Bus Arbitration:

This section is under construction.

PCI BIOS:

This section is under construction.
Contributor: Joakim 謌ren, Mark Sokos
Sources: Mark Sokos PCI page
Sources: "Inside the PCI Local Bus" by Guy W. Kendall, Byte, February 1994 v 19 p. 177-180
Sources: "The Indispensible PC Hardware Book" by Hans-Peter Messmer, ISBN 0-201-8769-3
Please send any comments to Joakim 謌ren.

Information from The Hardware Book

会员13288

英文的。我看不懂。。没卖过多少书。

会员12988

想学好主板，建议撑握一定的计算机英语单词，一般２０００多个

会员12212

够全面的，可惜都是英文，看不太明白。

会员3847

强烈支持2#，4#的答复。