- 积分
- 253
- 下载分
- 分
- 威望
- 点
- 原创币
- 点
- 下载
- 次
- 上传
- 次
- 注册时间
- 2009-10-13
- 精华
|
2#
发表于 2010-4-21 16:18:38
|
只看该作者
来自: 浙江宁波 来自 浙江宁波
找到该芯片的PDF。里面DDR的定义是这样的
DDR selection pin. If this pin is grounded, the device runs in DDR Mode. The error amplifier reference for VO2
is (VO1_VDDQ)/2, the REF_X output voltage becomes (VO1_VDDQ)/2 and skip mode is disabled for VO2,
Also, VREG5 is turned off when both ENBLx are at low in this mode. If this pin is at 2.2-V or higher, the device
runs in ordinary dual SMPS mode (dual mode), then the error amplifier reference for VO2 is connected to inter-
nal 0.85-V reference, the REF_X output voltage becomes 10 V, VREG5 is kept on regardless of ENBLchinafixtatus.
CAUTION: Do not toggle DDR while ENBL1 or ENBL2 are high. (See Table 2)
有点看不明白。 |
-
-
ps51020.pdf
555.5 KB, 下载次数: 224, 下载积分: 下载分 -2 分, 下载 1 次
|