广达台湾RD写的开机上电分析过程-英文的哦

会员478826

Plug AC,
→ALW power up, EC is ready    ->ok
→Press power button.         What happen when press power button?
1.     When press power button, over 200mS, EC will issue SIO_PWRBTN# to SB and delay 20mS to issue RSMRST#. (Please study by spec. to know what RSMRST function. It’ important)
2.     SB received RSMRST#, issue SLP_S3#/SLP_S4#/SLP_S5# to EC. EC base on SLP_S3/4/5# to enable SUS PWM IC for generator +5V_SUS and +3.3V_SUS and 1.8V_SUS. And PWM IC generator PWR GD signal feed back to EC.
Note:     A. The power turn on is high level to low level. Thus, should turn on 5V after 3V after 1.8V…
B. SB had SUS_REF pin, this pin had special requirement, need to read spec. to understand.
→EC starts to work,        
→SUS_ON, SUS，SUS_PWRGD power up, some block of SB starts work     
→RUN_ON, RUN, RUN_PWRGD power up, 1.05V_VCCP power up, then CPU, NB, SB and DDR are ready.  What happen between RUN_ON to CLK GEN. enable?
1.     EC issue RUN_ON, load SW MOSFET turn on 5V / 3.3V / 2.5V / 1.8V / 1.5V / 1.05V / 0.9V … (base on chipset requirement)
2.     Every RUN power OK, HW used all PWR GD to generator HWPG. HWPG to EC, EC issue IMVPVR ON to enable CPU power.
3.     When CPU power ready, PWM IC generator IMVP PWR GD.
Note:     A. The power turn on is high level to low level.
             B. SB had RUN_REF pin, this pin had special requirement, need to read spec. to understand.
             C. Why SB need SUS_REF and RUN_REF pins?
→CLOCK generator starts work and sends the clock to the main chipset. How CLK start work?
      CLK enable pin can used IMVP PWR GD because CPU power is last power in system.
      Note:     EE concept: power ready after get CLK after GET reset signal.
→Reset signals. How to generator reset signals?
1.     When EC issue IMVP VR ON, delay over 99mS to issue RESET_OUT#.
2.     EE tied RESET_OUT# & IMVP PWR GD by an AND gate to generator ICH_PWRGD.
3.     ICH_PWRGD link to SB and NB, SB received ICH_PWRGD, issue H_PWRGOOD to CPU.
4.     SB received ICH_PWRGD, issue PLTRST# to reset all IO and NB.
5.     NB received PLTRST# issue H_RESET# to reset CPU.
Note: From item 2 to item 5 timing is controlled by chipset.
→CPU gets the instructions from SPI ROM, then orders and co-work with NB, SB and DDR to do the work. What happen between CPU to BIOS(SPI ROM)?
1.     When CPU received H_RESET#, CPU will fetch 1st BIOS command.
2.     CPU via FSB to link NB and NB via DMI BUS link to SB.
3.     The SPI ROM had 2 places can be linked that are link to SB or link to EC.
4.     If SPI ROM link to SB, SB used SPI BUS to fetch BIOS command.
5.     If SPI ROM link to EC, SB via LPC BUS to EC, EC via SPI BUS to fetch BIOS command.
Note:     A. 1st command is FFF……0. (The F’s q’ty base on CPU support data bit)
             B. Why HW monitor ADS# can know BIOS workable or not? (Please find the answer by datasheet)
→MB BOOT.

If MB is no post, usually I’ll analyze it step by step as below: .
1.       Check if all the power are up, especially POWERGOOD and RESET signals;     What you lose in this step?
You should check clk had output or not and correct or not, after check reset signals.
2.       Check H_ADSTB# ;     What you lose in this step?
Check ADS# is confirm CPU had work or not. If ADS had work, it’s mean CPU to BIOS all BUS are ok, but fail on code, in this time, should transfer to BIOS debug.
If ADS hadn’t work, It’s mead CPU to BIOS BUS might some one fail. How should we need to check?
The easy way is check SPI BUS. Check SPI power had ready or not, check CE# confirm SPI ROM had been info start work, check clk had be output by SB(or EC), check DIN/DO.
Note: No post issue in HW and SW not easy to know this fail path, but base above method we can know what reason to change chipset.
3.       Re-flash EC CODE or re-flash BIOS;     This is be sure the fail by SW.
4.       Check DDR clock, if no signals, check the NB.       This should function fail not belong no post fail in my question.
5.       Check if the clocks from the clock generator are normal and find which part is abnormal, base on the abnormal part to analyze.  This should function fail analysis rule.
Note: A. For function fail, EE need to confirm power ok / clk ok / reset ok. And confirm POWER OK after CLK OK after reset signals OK.
B. For on stable function fail, HW can support SW to check with vendor for confirm the device setting correct or not.

会员480364

全英文发了有啥用，我要能看懂就不修本了。

会员283949

先弄下去了   慢慢看 哈哈

会员298317

好的，我有时间把它译为中文版的

会员383979

RD的东西你也能搞到不简单呀

会员355095

给个英文，我晕

会员458353

厉害··值得参考参考

会员702927

本人结合灵格斯翻译加上自己的理解：
Plug AC,( B+ m! x5 J* X$ E5 t# P9 i
→ALW power up, EC is ready    ->ok
→Press power button.         What happen when press power button?
1.     When press power button, over 200mS, EC will issue SIO_PWRBTN# to SB and delay 20mS to issue RSMRST#. (Please study by spec. to know what RSMRST function. It’ important)
当适配器插入后：
-》后缀名为ALW的电压都有了，且EC这一部分没问题了，就进入待机状态。
-》按下开机按钮  当按下开机按钮会发生什么事呢？
1. 当按下开机按钮200毫秒后，EC 将会产生SIO_PWRBTN#事件，也就是发送SIO_PWRBTN#（高低高）给南桥，并延迟20毫秒，发送RSMRST#（待机好）信号给南桥。
2.     SB received RSMRST#, issue SLP_S3#/SLP_S4#/SLP_S5# to EC. EC base on SLP_S3/4/5# to enable SUS PWM IC for generator +5V_SUS and +3.3V_SUS and 1.8V_SUS. And PWM IC generator PWR GD signal feed back to EC.
2. 当南桥的RSMRST信号没问题，SIO_PWRBN#信号也来了后，产生SLP_S3#/SLp_S4#/SLP_S5#事件给EC，EC得到这个信号，使待机芯片产生+5V_SUS,+3.3V_SUS和1.8V_SUS电压，电压产生后，PWM芯
芯片返回PWRGD（电压好）信号给EC。

会员702927

→EC starts to work,        
→SUS_ON, SUS，SUS_PWRGD power up, some block of SB starts work
SUS_ON后，所有SUS电压出来，然后发出SUS_PWRGD，南桥的某些模块开始工作。   
→RUN_ON, RUN, RUN_PWRGD power up, 1.05V_VCCP power up, then CPU, NB, SB and DDR are ready.  What happen between RUN_ON to CLK GEN. enable?
RUN_ON后，所有RUN电压出来，然后发出RUN_PWRGD，接着VCCP电压，CPU,南北桥，内存电压都准备好产生了。在RUN_ON至CLKGEN，这中间发生了什么呢？
1.     EC issue RUN_ON, load SW MOSFET turn on 5V / 3.3V / 2.5V / 1.8V / 1.5V /
1.05V / 0.9V … (base on chipset requirement)
EC产生RUN_ON，使开关管转化成5V/3.3V/2.5V/1.8V/1.5V/1.05V/0.9V，这个是基于芯片的需要，比如CPU供电芯片需要的。
2.     Every RUN power OK, HW used all PWR GD to generator HWPG. HWPG to EC, EC issue IMVPVR ON to enable CPU power.4 a. C. `5 ]% s4 @" b
每一个RUN状态的电压都生产了后，发出的PG信号，合在一起产生HWPG，HWPG发送给EC，EC产生IMVPVRON来开启CPU供电。
3.     When CPU power ready, PWM IC generator IMVP PWR GD.
当CPU电压准备好后，PWM芯片产生IMVPPWRGD。

会员702927

Note:     A. The power turn on is high level to low level.. p# b! A' d) u& \; e8 h4 X
             B. SB had RUN_REF pin, this pin had special requirement, need to read spec. to understand.: T. _" g; [& \' U' o3 r, U6 G
SB有一个RUN_REF引脚，这个脚有特殊的需要，需要EC读取配置指定，才能知道具体的意思。
             C. Why SB need SUS_REF and RUN_REF pins?" Z* [: i4 R! K1 t
           为什么SB需要SUS_REF和RUN_REF脚呢？
→CLOCK generator starts work and sends the clock to the main chipset. How CLK start work?
时钟芯片开始工作，发出各组时钟给芯片，时钟是怎样开始工作？
      CLK enable pin can used IMVP PWR GD because CPU power is last power in system.# T9 q0 W$ n) @, p- L3 q0 {" w
时钟芯片有一个开启脚，由IMVPPWRGD来开启，因为CPU电压是系统最后一个产生的供电。
      

会员702927

→Reset signals. How to generator reset signals?
复位信号，复位信号是怎样产生的？
1.     When EC issue IMVP VR ON, delay over 99mS to issue RESET_OUT#.
当EC发出IMVPVRON，在99毫秒后发出RESET_OUT#。
2.     EE tied RESET_OUT# & IMVP PWR GD by an AND gate to generator ICH_PWRGD.: J9 {- }8 N& N" N
EE把REST_OUTt#和IMVPPWRGD合在一起（与门），产生ICH_PWRGD信号。
3.     ICH_PWRGD link to SB and NB, SB received ICH_PWRGD, issue H_PWRGOOD to CPU./ t; y0 |; j5 g& o% D, x. J' d
SB收到ICH_PWRGD后，发出H_PWRGOOD给CPU
4.     SB received ICH_PWRGD, issue PLTRST# to reset all IO and NB.
接着发出PLTRST#复位所有IO和北桥。
5.     NB received PLTRST# issue H_RESET# to reset CPU.
北桥收到PLTRST#发出H_RESET#复位CPU。

会员702927

→CPU gets the instructions from SPI ROM, then orders and co-work with NB, SB and DDR to do the work. What happen between CPU to BIOS(SPI ROM)?
CPU得到从BIOS那里的指示后，然后发出命令与南北桥内存开始工作，在CPU和BIOS之间发生了什么呢？
1.     When CPU received H_RESET#, CPU will fetch 1st BIOS command./ g! Y( H' c- N' y5 [. j
当CPU复位后，CPU将得到第一条BIOS命令。
2.     CPU via FSB to link NB and NB via DMI BUS link to SB.
CPU通过FSB总线连接北桥，北桥通过DMI总线连接SB。
3.     The SPI ROM had 2 places can be linked that are link to SB or link to EC.
SPI的BIOS有两个方式访问，第一种是SB直接连接，第二种是SB通过EC去访问BIOS。
4.     If SPI ROM link to SB, SB used SPI BUS to fetch BIOS command.& ^# w% l. f0 ]/ I" U, W: L2 ~
如果直接SB连接，使用SPI总线去访问BIOS
5.     If SPI ROM link to EC, SB via LPC BUS to EC, EC via SPI BUS to fetch BIOS command.2
通过EC连接，SB通过LPC总线访问EC，EC现通过SPI总线访问BIOS，得到BIOS命令。

会员702927

Note:     A. 1st command is FFF……0. (The F’s q’ty base on CPU support data bit)# D) K) u; x4 w- U  I6 [/ R
第一条命令，诊断卡显示FFFF
             B. Why HW monitor ADS# can know BIOS workable or not? (Please find the answer by datasheet)
为什么能通过ADS#信号，知道BIOS有没问题？(请自己查数据手册）
if MB is no post, usually I’ll analyze it step by step as below: .
如果MB没自检，通过我将像下面一样一步一步的分析。
1.       Check if all the power are up, especially POWERGOOD and RESET signals;     What you lose in this step?
检查是否所有的电压都出来了，尤其是POWERGOOD和RESET信号。
You should check clk had output or not and correct or not, after check reset signals.
你应该检查时钟有没有输出，正常与否，然后检查复位信号。
2.       Check H_ADSTB# ;     What you lose in this step?; }: Y5 b0 g. f: m
检查H_ADSTB#信号
Check ADS# is confirm CPU had work or not. If ADS had work, it’s mean CPU to BIOS all BUS are ok, but fail on code, in this time, should transfer to BIOS debug.
检查ADS#信号确认CPU是否工作，如果ADS正常连续工作，它表示CPU到BIOS之前的所有总线OK。
If ADS hadn’t work, It’s mead CPU to BIOS BUS might some one fail. How should we need to check?
如果ADS没有，表示CPU到BIOS的总线有问题，该怎么去判断呢？
The easy way is check SPI BUS. Check SPI power had ready or not, check CE# confirm SPI ROM had been info start work, check clk had be output by SB(or EC), check DIN/DO. ! X& V/ c7 G! p3 V' A
比较简单的方法是去检查SPI总线，检查SPI有没有电压，检查CE#信号确认BIOS芯片开始工作，

会员834228

飘过 参观下

会员829337

本想发个翻译没想到都有人发出来了