迅维实地笔记本学员研究成果--ISL6267SVI部分的翻译与APU的SVID波形判断

会员204454

SVI接口时序:典型" PRE-PWROK METAL VID" 启动

SVI INTERFACE: TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP

表格1." PRE-PWROK METAL VID" 代码

SVC	SVD	输出电压(V)
0	0	1.1
0	1	1.0
1	0	0.9
1	1	0.8

内置的DAC(数模转换)电路开始上升核心,北桥VRs(电压调节器)来解码" pre-PWROK METAL VID" 的输出电平.

The internal DAC circuitry begins to ramp Core and Northbridge VRs to the decoded pre-PWROK Metal VID output level.

数字软启动电路上升内部基准到大约为2mV/μs的固定值目标.

The digital soft-start circuitry ramps the internal reference to the target gradually at a fixed rate of approximately 2mV/μs.

这个上升控制给所有电压层降低软启动时的浪涌电流.

The controlled ramp of all output voltage planes reduces in-rush current during the soft-start interval.

在软启动结束间隔,PGOOD输出为高,表示所有输出层已达到稳定电压极限.

At the end of the soft-start interval, the PGOOD output transitions high, indicating all output planes are within regulation limits.

如果ENABLE(开启)输入低于启用下降的阈值,ISL6267高阻态两路输出.

If the ENABLE input falls below the enable falling threshold, the ISL6267 tri-states both outputs.

在失去ENABLE时PGOOD拉低.核心和北桥层基于输出电容和负载漏泄电阻衰减.

PGOOD is pulled low with the loss of ENABLE. The Core and Northbridge planes decay, based on output capacitance and load leakage resistance.

如果Vcc降低到POR(POWR ON REST,上电复位)水平,ISL6267会已以上所描述的方式进行响应.

If bias to VCC falls below the POR level, the ISL6267 responds in the manner previously described.

一旦Vcc和ENABLE上升到高于相应的上升阈值时,内部的DAC电路重新获取一个" pre-PWROK METAL VID" 并控制软启动

Once VCC and ENABLE rise above their respective rising thresholds, the internal DAC circuitry reacquires a pre-PWROK metal VID code, and the controller soft-starts.

Vfix(电压固定)模式

VFIX Mode

ISL6267不支持Vfix模式, 在主板上无CPU并ISL6267开启时,SVC和SVD的状态设置为"pre-PWROK METAL VID" 并开始软启动.

The ISL6267 does not support VFIX Mode. In the event a CPU is not present on a motherboard and the ISL6267 is powered on, the state of SVC and SVD sets the pre-PWROK metal VID as the “Pre-PWROK Metal VID” on page 16 and begins soft-starting.

SVI模式

SVI Mode

一旦控制器以成功软启动,PGOOD和PGOOD_NB为高.处理器可以发出PWROK信号,通知ISL6267来准备接收SVI指令.

Once the controller has successfully soft-starts and PGOOD and PGOOD_NB transition high, the processor can assert PWROK to signal the ISL6267 to prepare for SVI commands.

控制器主动监视SVI接口设置VID指令,移动层电压来启动VID值.

The controller actively monitors the SVI interface for set VID commands to move the plane voltages to start-up VID values.

在" AMD Design Guide for Voltage Regulator Controllers Accepting Serial VID Codes" 规范中有SVI总线协议的详情.

Details of the SVI Bus protocol are provided in the “AMD Design Guide for Voltage Regulator Controllers Accepting Serial VID Codes” specification.

一旦收到设置的VID指令,ISL6267解码信息,并确定哪些VR(电压调节器)受令和哪个VID目标是需要的(见表格2).

Once a set VID command is received, the ISL6267 decodes the information to determine which VR is affected and which VID target is required (see Table 2).

内置DAC电路步骤操作受令VR输出电压到新VID水平.

The internal DAC circuitry steps the output voltage of the VR commanded to the new VID level. During this time, one or more of the VR outputs could be targeted.

在这个时间里,一个或更多的VR输出可以为目标.在任何情况下VR被Serial VID (SVID,)指令关闭时,PGOOD信号仍然有效.

In the event either VR is commanded to power-off by serial VID commands, the PGOOD signal remains asserted.

如果PWROK输入停止,该控制器步骤操作核心和北桥VR返回到在最初软启动时已寄存的" pre-PWROK METAL VID" 水平.

If the PWROK input is de-asserted, then the controller steps both the Core and the Northbridge VRs back to the stored pre-PWROK metal VID level in the holding register from initial soft-start.

不尝试在此期间读取SVC和SVD的输入.如果PWROK重新输入.板载SVI接口会等待设置VID指令.

No attempt is made to read the SVC and SVD inputs during this time. If PWROK is re-asserted, then the on-board SVI interface waits for a set VID command.
如果正常运行期间中ENABLE被拉低时,所有内置驱动为高阻态并拉低PGOOD.

If ENABLE goes low during normal operation, all internal drivers are tri-stated and PGOOD is pulled low.

也会清除“pre-PWROK METAL VID” METAL VID代码.在控制器强制检查SVC和SVD后重新启动.

This event clears the pre-PWROK metal VID code and forces the controller to check SVC and SVD upon restart.

在Vcc或Vin正常运行期间时上电复位(POR)时,会关闭两路稳压器并拉低两个PGOOD输出.不会保留" pre-PWROK METAL VID" 代码.

A POR event on either VCC or VIN during normal operation shuts down both regulators, and both PGOOD outputs are pulled low. The pre-PWROK metal VID code is not retained.

会员461209

嗯 不错学习了，， ，，

会员204454

VID自适应转换

VID-on-the-Fly Transition

一旦PWROK为高,ISL6267检测到这个操作并开始为SVI指令监控SVC和SVD脚位.

Once PWROK is high, the ISL6267 detects this flag and begins monitoring the SVC and SVD pins for SVI instructions.

微处理器遵循在以下部分中列出的协议,来发出VID自适应转换的指令.

The microprocessor follows the protocol outlined in the follow ingsections to send instructions for the VID-on-the-fly transitions.
ISL6267解码指令并确认新VID代码.当新VID代码比当前VID水平高时,

The ISL6267 decodes the instruction and acknowledges the new VID code. For the VID codes higher than the current VID level,
ISL6267步骤操作受令VR以7.5mV/μs的典型压摆率输出新的VID目标,以符合AMD的要求.

the ISL6267 begins stepping the commanded VR outputs to the new VID target with a typical slew rate of 7.5mV/μs, which meets the AMD requirements.

当新VID代码低于当前VID水平,ISL6267会检查PSI_L的状态.

When the VID codes are lower than the current VID level, the ISL6267 checks the state of PSI_L.

如果PSI_L为高,控制器会开始步骤操作稳压器以-7.5mV/μs的典型压摆率输出新的VID目标.

If PSI_L is high, the controller begins stepping the regulator output to the new VID target with a typical slew rate of -7.5mV/μs.

如果PSI_L为低,控制器允许输出电压衰减,缓慢步骤操作DAC与输出自然衰减下降.

If PSI_L is low, the controller allows the output voltage to decay and slowly steps the DAC down with the natural decay of the output.

这使得控制器收到命令时能迅速恢复和移动到高VID代码.

This allows the controller to quickly recover and move to a high VID code if commanded.

AMD要求在这些条件下不需要调节器去满足-5mV/μs.的最小压摆率规范。

AMD requirements under these conditions do not require the regulator to meet the minimum slew rate specification of -5mV/μs

在两种条件下.压摆率不允许超过10mV/μs.

In either case, the slew rate is not allowed to exceed 10mV/μs.

1.ISL6267没有改变PGOOD状态(在AMD规范中为VCCPWRGD)

The ISL6267 does not change the state of PGOOD (VCCPWRGD in AMD specifications)

2.当有一个VID自适应转换进行时.

when a VID-on-the-fly transition occurs.

SVI有线协议

SVI WIRE Protocol

SVI有线协议是基于I2C总线概念,两条线(串行时钟SVC和串行数据SVD).

The SVI WIRE protocol is based on the I2C bus concept Two wires [serial clock (SVC) and serial data (SVD)],

在AMD处理器(Master,主)与VR控制器(Slave,从)的总线上传输信息.

carry information between the AMD processor (master) and the VR controller (slave) on the bus.

Master在事务中开始和结束SVI事务并驱动时钟,SVC.

The master initiates and terminates SVI transactions and drives the clock, SVC, during a transaction

Salve接收 SVI事务并采取相应的行动.

The slave receives the SVI transactions and acts accordingly.

(AMD处理器总是Master, VR控制器是Slave.)

The AMD processor is always the master, and the voltage regulators are the slaves.

移动SVI有线协议时序是基于I2C的高速模式,详情请看AMD publication #40182文件

Mobile SVI WIRE protocol timing is based on high-speed mode I2C. See AMD publication #40182 for additional details.

表格2:SVID代码

登录/注册后看高清大图

图1:发送字节实例:

登录/注册后看高清大图

SVI总线协议

SVI Bus Protocol

AMD的处理器总线协议是符合" SMBus(系统管理总线)发送字节协议" 发送VID数据（参见图1）。

The AMD processor bus protocol is compliant with SMBus send byte protocol for VID transactions (see Figure 14).

发送字节数据时,处理器发出开始序列,随后发出后受令VR的从地址.

During a send byte transaction, the processor sends the start sequence followed by the slave address of the VR for which the VID command applies.

地址字节必须根据表格3中配置.

The address byte must be configured according to Table 3.

处理器然后发出写位,写位之后如果ISL6267收到了有效地址位会发出应答位,处理器然后在数据阶段中发出PSI-L位和VID位.

The processor then sends the write bit. After the write bit, if the ISL6267 receives a valid address byte, it sends the acknowledge bit. The processor then sends the PSI-L bit and VID bits during the data phase.

(串行VID8位数据字段编码在表格4中概述.)

The Serial VID 8-bit data field encoding is outlined in Table 4

如果ISL6267在数据阶段中收到有效8位代码会发出应答位.

If the ISL6267 receives a valid 8-bit code during the data phase, it sends the acknowledge bit.

最终,CPU发出停止序列,随后IS6267检测到停止.然后可以进行VID自适应转换.

Finally, the processor sends the stop sequence. After the ISL6267 has detected the stop, it can then proceed with the VID-on-the-fly transition.

表格3.SVI发送位地址解释

位	解释
6:4	总是110
3	为AMD以后预留
2	VDD1;如果设置，那么下面的数据字节包含VID为   VDD1[注：ISL6267
1	VDD0;如果设置，那么下面的数据字节包含VID为   VID0
0	VDDNB;如果设置则下列数据字节包含VID为   VIDNB

表格4.SVID 8位字段编码

位	解释
7	PSI_L    =0意味该处理器是一个稳压器进入省电模式的最佳负载    =1 意味该处理器不是一个稳压器进入省电模式的最佳负载
6:0	SVID[6:0]可在表格2定义.

操作

Operation

在启动序列之后.ISL6267开始调节核心与北桥输出电压到以设定的" pre-PWROK METAL VID" .

After the start-up sequence, the ISL6267 begins regulating the Core and Northbridge output voltages to the pre-PWROK metal VID programmed.

控制器监视SVI命令到进入省电模式之前,实行动态VID变化并关闭单个输出.

The controller monitors SVI commands to determine when to enter power-saving mode, implement dynamic VID changes, and shut down individual outputs.

以黄老师抓到的APU波形为例:

登录/注册后看高清大图

我们可以知道这个APU是这样的....

VID0供电,电压1.0375V,不支持省电模式...

AMD的APU都是以这个标准来使用SVID的,

如果有新的svid方式出现可以在这个cpu的供电芯片手册里找到相应的资料.

如果有问题请PM我,以便及时改正

ISL6267数据手册:

isl6267.pdf (1.12 MB, 下载次数: 10)

2015-5-22 23:31 上传

点击文件名下载附件

黄老师抓到的APU波形:

http://www.chinafix.com/thread-833800-1-1.html

会员957643

学习了，得好好研究研究了

会员800200

我只能说，我完全没看明白，看来我的补课了，

会员368751

占个沙发 ，这不是我的研究范围之内。完全看不懂

会员928370

看不懂，要实地了

会员371953

学习了，得好好研究研究了

会员919913

纯理论技术贴，不错，没事的时候都可以研究下。有好处。

会员896469

根本一点看不懂，实地的就是不一样

会员968512

新手路上，涨涨知识。

会员422487

这是把芯片内部英文翻译了一篇，不错，。

会员998649

这个资料是迅维的资料吧 有迅维水印

SVID在维修中真正需要解码的不多  做技术研究可以深解

会员204454

神佑 发表于 2015-5-23 15:34
这个资料是迅维的资料吧 有迅维水印

SVID在维修中真正需要解码的不多  做技术研究可以深解

个人翻译,只是数据手册里带水印而已.
搞维修吧,最大的乐趣就是在研究啊.

会员894671

感觉好复杂的

会员804903

不错 有学到了啊

会员805094

谢谢共享同学

会员623900

一点都看不懂啊

会员789542

有点懂了，需要研究下

会员951488

太专业了，大部分观众都该补补课了。