马上注册，获取阅读精华内容及下载权限
您需要 登录 才可以下载或查看，没有帐号？注册
x
BIOS读写时总线上的电平状态 10.2.4 Write Enable (06h) The Write Enableinstruction (Figure 4) sets the Write Enable Latch (WEL) bit in the StatusRegister to a 1. The WEL bit must be set prior to every Page Program, SectorErase, Block Erase, Chip Erase and Write Status Register instruction. The WriteEnable instruction is entered by driving /CS low, shifting the instruction code“06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving/CS high. 写入允许指令（见图4）将写入允许位（WEL）设置为1。 1. 写入允许位必须在每次页程序、分区擦除、块擦除、芯片擦除和写入状态寄存器指令之前设置。写入允许指令由低电压驱动/CS，输入代码 “06h”到数据输入（DI）信号线的上升沿，并且再次驱动/CS高。
10.2.5 Write Disable (04h) The WriteDisable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in theStatus Register to a 0. The Write Disable instruction is entered by driving /CSlow, shifting the instruction code “04h” into the DI pin and then driving /CShigh. Note that the WEL bit is automatically reset after Power-up and uponcompletion of the Write Status Register, Page Program, Sector Erase, BlockErase and Chip Erase instructions. 写入禁用指令（见图4）重置了WriteEnable Latch（WEL）位在状态寄存器中为0。 1. 写入禁用指令由低电压驱动/CS，输入代码“04h”到数据输入（DI）信号线，并且再次驱动/CS高。 注意：write enable latch 位会自动重置在功放启动后和写入状态寄存器、页程序、分区擦除、块擦除和芯片擦除指令完成之后。 10.2.6 Read Status Register-1 (05h) andRead Status Register-2 (35h) The Read Status Register instructions allow the8-bit Status Registers to be read. The instruction is entered by driving /CSlow and shifting the instruction code “05h” for Status Register-1 and “35h” forStatus Register-2 into the DI pin on the rising edge of CLK. The statusregister bits are then shifted out on the DO pin at the falling edge of CLKwith most significant bit (MSB) first as shown in figure 6. The Status Registerbits are shown in figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC,SRP0, SRP1 and QE bits (see description of the Status Register earlier in thisdatasheet). The Status Register instruction may be used at any time, even whilea Program, Erase or Write Status Register cycle is in progress. This allows theBUSY status bit to be checked to determine when the cycle is complete and ifthe device can accept another instruction. The Status Register can be readcontinuously, as shown in Figure 6. The instruction is completed by driving /CShigh 读取状态寄存器指令（见图4）允许8位状态寄存器被读取。指令由低电压驱动/CS，然后输入代码“05h”到状态寄存器-1，和“35h”到状态寄 存器-2的 instruccioncode 到数据输入（DI）信号线上，于 CLK上升沿完成。 然后状态寄存器位在DO线上在CLK下降缘以 MSB 的方式输出。状态寄存器的位图见图3a和3b，并包含BUSY、WEL、BP2-BO、TB、SEC、SRP0、SRP1 和 QE位 (请参考状态寄存器描述，以下文档中的早期数据表）。 状态寄存器指令可以在任何时候使用，即使正在进行程序、擦除或写入状态寄存器的周期。这个功能允许检查BUSY状态位来确定周期是否完成，并判断设备是否可以接受另一个指令。状态寄存器可以持续读取，如图6所示。指令完成时，驱动/CS高即可完成。 注意：状态寄存器指令可以在任何时候使用，即使正在进行写入状态寄存器、页程序、擦除或其他指令周期。
10.2.7 Write Status Register (01h) TheWrite Status Register instruction allows the Status Register to be written. AWrite Enable instruction must previously have been executed for the device toaccept the Write Status Register Instruction (Status Register bit WEL mustequal 1). Once write enabled, the instruction is entered by driving /CS low,sending the instruction code “01h”, and then writing the status register databyte as illustrated in figure 7. The Status Register bits are shown in figure 3and described earlier in this datasheet. Only non-volatile Status Register bitsSRP0, SEC, TB, BP2, BP1, BP0 (bits 7, 5, 4, 3, 2 of Status Register-1) and QE,SRP1(bits 9 and 8 of Status Register-2) can be written to. All other StatusRegister bit locations are read-only and will not be affected by the WriteStatus Register instruction. The /CS pin must be driven high after the eighthor sixteenth bit of data that is clocked in. If this is not done the WriteStatus Register instruction will not be executed. If /CS is driven high afterthe eighth clock (compatible with the 25X series) the QE and SRP1 bits will becleared to 0. After /CS is driven high, the self-timed Write Status Registercycle will commence for a time duration of tW (See AC Characteristics). Whilethe Write Status Register cycle is in progress, the Read Status Registerinstruction may still be accessed to check the status of the BUSY bit. The BUSYbit is a 1 during the Write Status Register cycle and a 0 when the cycle isfinished and ready to accept other instructions again. After the Write Registercycle has finished the Write Enable Latch (WEL) bit in the Status Register willbe cleared to 0. The Write Status Register instruction allows the Block Protectbits (SEC, TB, BP2, BP1 and BP0) to be set for protecting all, a portion, ornone of the memory from erase and program instructions. Protected areas becomeread-only (see Status Register Memory Protection table and description). TheWrite Status Register instruction also allows the Status Register Protect bits(SRP0, SRP1) to be set. Those bits are used in conjunction with the WriteProtect (/WP) pin, Lock out or OTP features to disable writes to the statusregister. Please refer to 10.1.16 for detailed descriptions regarding StatusRegister protection methods. Factory default for all status Register bits are0. 写入状态寄存器指令（见图4）允许状态寄存器被写入。 Write Enable 指令必须在device中先执行，才能接受Write Status RegisterInstruction（状态寄存器位WEL必须等于1）。一旦写入允许，指令进入时驱动/CS低，输入代码“01h”，然后写入状态寄存器数据字节，如图7所示。状态寄存器的位图见图3，并在该文档中早期描述。 只能非可变性状态寄存器位SRP0, SEC, TB, BP2, BP1, BP0（状态寄存器-1的位数 7、5、4、3、2）和 QE, SRP1（状态寄存器-2的位数9 和8）可以写入。其他所有状态寄存器位位均为读-only，会不会受到Write Status Register指令的影响不变。 /CS线必须在数据时钟中第八或第十六个位进行驱动高，如果不做则 Write Status Register指令将不会执行。如果/CS在 eighth时钟（与25X系列兼容）驱动高，则 QE和SRP1位会清零。写状态寄存器周期完成后，self-timed Write Status Register的cycle会开始，并持续时间为 tW（见AC特性）。在写状态寄存器周期中，Read状态寄存器指令可以访问BUSY状态位检查其状态。BUSY状态位为1在写状态寄存器周期内，0结束后并且能够接受其他指令时。 写状态寄存器指令允许设置块保护位（SEC, TB, BP2, BP1和BP0），保护所有、部分或无任何的内存从擦除和程序指令。保护区域成为了不可读（见状态寄存器的表格和描述）。 Write状态寄存器指令还允许设置状态寄存器保护位（SRP0，SRP1）。这些位与/WP线、加锁或OTP功能共同使用，以禁用状态寄存器写入。请参阅10.1.16有关状态寄存器保护方法的详细描述。actory(default值为所有状态寄存器位均为0)
10.2.8 Read Data (03h) The Read Datainstruction allows one more data bytes to be sequentially read from the memory.The instruction is initiated by driving the /CS pin low and then shifting theinstruction code “03h” followed by a 24-bit address (A23-A0) into the DI pin.The code and address bits are latched on the rising edge of the CLK pin. Afterthe address is received, the data byte of the addressed memory location will beshifted out on the DO pin at the falling edge of CLK with most significant bit(MSB) first. The address is automatically incremented to the next higheraddress after each byte of data is shifted out allowing for a continuous streamof data. This means that the entire memory can be accessed with a singleinstruction as long as the clock continues. The instruction is completed bydriving /CS high. The Read Data instruction sequence is shown in figure 8. If aRead Data instruction is issued while an Erase, Program or Write cycle is inprocess (BUSY=1) the instruction is ignored and will not have any effects onthe current cycle. The Read Data instruction allows clock rates from D.C. to amaximum of fR (see AC Electrical Characteristics). 读取数据指令（见图8）允许从内存中进一步读取一个字节。指令启动由驱动/CS线低，然后输入代码“03h”followed by 24-bit 地址（ A23-A0）向DI pin。代码和地址位均在CLK上升缘被拉提。在接收完成后，所对应的内存位置的数据字节将在DO线上在CLK下降缘以 MSB 的方式 输出。地址将自动增加到下一个高位地址每个字节数据出现在 DO 线上的允许持续数据流。这种情况下，只要钟继续运行，则可以用单个指令 访问整个内存。指令完成时驱动/CS高即可完成。读取数据指令序列见图8。如果在执行写擦程、程序或写状态寄存器周期期间（BUSY=1）发起 Read Data指令，指令将被忽略，并不会对当前周期产生任何影响。读取数据指令允许从 DC到最大fR（见AC电气特性）的钟频率访问内存。 10.2.9 Fast Read (0Bh) The Fast Readinstruction is similar to the Read Data instruction except that it can operateat the highest possible frequency of FR (see AC Electrical Characteristics).This is accomplished by adding eight “dummy” clocks after the 24-bit address asshown in figure 9. The dummy clocks allow the devices internal circuitsadditional time for setting up the initial address. During the dummy clocks thedata value on the DO pin is a “don’t care”. 快速读指令与Read Data指令相似，但它可以在最高可能的频率FR（见AC电气特性）上运行。这种情况是通过在图9中显示的24位地址后添加八 个“Dummy”时钟实现的。Dummy时钟允许设备内部电路获得为设置初始地址做准备的额外时间。在 dummy 时钟期间，DO线上的数据值为“不在乎”。 10.2.10 Fast Read Dual Output (3Bh) TheFast Read Dual Output (3Bh) instruction is similar to the standard Fast Read(0Bh) instruction except that data is output on two pins; IO0 and IO1. Thisallows data to be transferred from the W25Q80/16/32 at twice the rate ofstandard SPI devices. The Fast Read Dual Output instruction is ideal forquickly downloading code from Flash to RAM upon power-up or for applicationsthat cache code segments to RAM for execution. Similar to the Fast Readinstruction, the Fast Read Dual Output instruction can operate at the highestpossible frequency of FR (see AC Electrical Characteristics). This isaccomplished by adding eight “dummy” clocks after the 24-bit address as shownin figure 10. The dummy clocks allow the device's internal circuits additionaltime for setting up the initial address. The input data during the dummy clocksis “don’t care”. However, the IO0 pin should be high-impedance prior to thefalling edge of the first data out clock. 快速读双输出（3Bh）指令与标准的快速读（0Bh）指令相似，但它会将数据在两个线上输出：IO0和IO1。这允许从W25Q80/16/32设备中以标准 SPI设备比速度快两倍的速率传输数据。快速读双输出指令是适合快速下载Flash到RAM上的代码或为执行而缓存代码段到RAM的应用。 与快速读指令相似，快速读双输出指令可以在最高可能的频率FR（见AC电气特性）上运行。这是通过在图10中显示的24位地址后添加八个“ Dummy”时钟实现的。 Dummy时钟允许设备内部电路获得为设置初始地址做准备的额外时间。在 dummy 时钟期间，输入数据为“不关心”。但是，IO0线应在第一数据输出时钟下降缘前保持高阻抗。 10.2.11 Fast Read Quad Output (6Bh) TheFast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output(3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, andIO3. A Quad enable of Status Register-2 must be executed before the device willaccept the Fast Read Quad Output Instruction (Status Register bit QE must equal1). The Fast Read Quad Output Instruction allows data to be transferred fromthe W25Q80/16/32 at four times the rate of standard SPI devices. The Fast ReadQuad Output instruction can operate at the highest possible frequency of FR(see AC Electrical Characteristics). This is accomplished by adding eight“dummy” clocks after the 24-bit address as shown in figure 11. The dummy clocksallow the device's internal circuits additional time for setting up the initialaddress. The input data during the dummy clocks is “don’t care”. However, theIO pins should be high-impedance prior to the falling edge of the first dataout clock. 快速读四输出（6Bh）指令与快速读双输出（3Bh）指令相似，但它会将数据在四个线上输出：IO0、IO1、IO2和IO3。Quad启 StatusRegister-2指令必须执行，否则设备才会接受快速读四输出指令（Status Register bit QE必须等于1）。快速读四输出指令允许从W25Q80/16/32设备中以标准SPI设备比速度快四倍的速率传输数据。 快速读四输出指令可以在最高可能的频率FR（见AC电气特性）上运行。这是通过在图11中显示的24位地址后添加八个“Dummy”时钟实现的。 Dummy时钟允许设备内部电路获得为设置初始地址做准备的额外时间。在 dummy 时钟期间，输入数据为“不关心”。但是，IO线应在第一数据 输出时钟下降缘前保持高阻抗。 10.2.12 Fast Read Dual I/O (BBh) The FastRead Dual I/O (BBh) instruction allows for improved random access whilemaintaining two IO pins, IO0 and IO1. It is similar to the Fast Read DualOutput (3Bh) instruction but with the capability to input the Address bits(A23-0) two bits per clock. This reduced instruction overhead may allow forcode execution (XIP) directly from the Dual SPI in some applications. To ensureoptimum performance the High Performance Mode (HPM) instruction (A3h) must beexecuted once, prior to the Fast Read Dual I/O Instruction. The Fast Read DualI/O instruction can further reduce instruction overhead through setting theMode bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a.The upper nibble of the Mode (M7-4) controls the length of the next Fast ReadDual I/O instruction through the inclusion or exclusion of the first byteinstruction code. The lower nibble bits of the Mode (M3-0) are don’t care(“x”). However, the IO pins should be high-impedance prior to the falling edgeof the first data out clock. If the Mode bits (M7-0) equals “Ax” hex, then thenext Fast Read Dual I/O instruction (after /CS is raised and then lowered) doesnot require the BBh instruction code, as shown in figure 12b.. This reduces theinstruction sequence by eight clocks and allows the address to be immediatelyentered after /CS is asserted low. If the Mode bits (M7-0) are any value otherthan “Ax” hex, the next instruction (after /CS is raised and then lowered)requires the first byte instruction code, thus returning to normal operation. AMode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuingnormal instructions (See 10.2.28 for detailed descriptions). 快速读双IO（BBh）指令允许改善随机访问，而保持两个IO线：IO0和IO1。它与快速读双输出（3Bh）指令相似，但具有输入地址位（A23-0）每个时钟两位。这减少的指令过载可能使得在某些应用中直接从Dual SPI执行代码（XIP）。为了确保最佳性能，高-performance模式（HPM）指令（A3h）必须先执行一次，在快速读双IO指令之前。 快速读双IO指令可以进一步减少指令过载通过设置模式位（M7-0）后输入地址位（A23-0），如图12a所示。模式位的上 nibble（M7-4）控制下一个快速读双IO指令的长度，通过包含或排除第一个字节指令代码来实现。在模式位的下 nibble（M3-0）中， bits 为“不关心”（x）。但是，IO线应在第一数据输出时钟下降缘前保持高阻抗。 如果模式位（M7-0）等于“Ax””，则下一个快速读双IO指令（在/Cs被升高后和再次降低）不需要BBh指令代码，如图12b所示。这将instruction序列减少八个时钟，并允许在/Cs被assert低后立即输入地址。 如果模式位（M7-0）不是“Ax”，则下一个指令（在/Cs被升高后 和再次降低）需要第一字节指令代码，因此恢复正常操作。一个模式位Reset指令可以用来reset模式位（M7-0）在发出普通指令之前（见10.2.28 for详细描述）。 10.2.13 Fast Read Quad I/O (EBh) The FastRead Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh)instruction except that address and data bits are input and output through fourpins IO0, IO1, IO2 and IO3 and four Dummy clock are required prior to the dataoutput. The Quad I/O dramatically reduces instruction overhead allowing fasterrandom access for code execution (XIP) directly from the Quad SPI. The QuadEnable bit (QE) of Status Register-2 must be set to enable the Fast read QuadI/O Instruction. To ensure optimum performance the High Performance Mode (HPM)instruction (A3h) must be executed once, prior to the Fast Read Quad I/OInstruction. The Fast Read Quad I/O instruction can further reduce instructionoverhead through setting the Mode bits (M7-0) after the input Address bits(A23-0), as shown in figure 13a. The upper nibble of the Mode (M7-4) controlsthe length of the next Fast Read Quad I/O instruction through the inclusion orexclusion of the first byte instruction code. The lower nibble bits of the Mode(M3-0) are don’t care (“x”). However, the IO pins should be high-impedanceprior to the falling edge of the first data out clock. If the Mode bits (M7-0)equals “Ax” hex, then the next Fast Read Quad I/O instruction (after /CS israised and then lowered) does not require the EBh instruction code, as shown infigure 13b. This reduces the instruction sequence by eight clocks and allowsthe address to be immediately entered after /CS is asserted low. If the Modebits (M7-0) are any value other than “Ax” hex, the next instruction (after /CSis raised and then lowered) requires the first byte instruction code, thusreturning to normal operation. A Mode Bit Reset instruction can be used toreset Mode Bits (M7-0) before issuing normal instructions (See 10.2.28 fordetailed descriptions). 快速读四输出（EBh）指令与快速读双输出（BBh）指令相似，但输入和输出地址位和数据位通过四个线IO0、IO1、IO2和IO3，并且在数据输出 前需要四个Dummy时钟。 QuadI/O significantly 减少了指令过载，允许更快的随机访问，从而直接执行代码（XIP）从Quad SPI中。Quad I/OEnable bits（QE）是状态寄存器-2的Bit必须设置以启用Fastread Quad I/O Instruction。为了确保最佳性能，高性能模式（HPM）指令 （A3h）必须先执行一次，在快速读四输出指令之前。 快速读四输出指令可以进一步减少指令过载通过设置模式位（M7-0）后输入地址位（A23-0），如图13a所示。模式位的上nibble（M7-4）控制 下一个快速读四输出指令的长度，通过包含或排除第一个字节指令代码来实现。在模式位的下nibble（M3-0）中，bits 为“不关心”（x）。 但是，IO线应在第一数据输出时钟下降缘前保持高阻抗。 如果模式位（M7-0）等于“Ax” hexadecimal，则下一个快速读四输出指令（在/Cs被升高后和再次降低）不需要EBh指令代码，如图13b所示。 这将instruction序列减少八个时钟，并允许在/Cs被assert低后立即输入地址。 如果模式位（M7-0）不是“Ax”hexadecimal，则下一个指令 （在/Cs被升高后和再次降低）需要第一字节指令代码，因此恢复正常操作。一个模式位Reset指令可以用来reset模式位（M7-0）在发出普通指 令之前（见10.2.28 for详细描述）。 10.2.14 Page Program (02h) The Page Programinstruction allows from one byte to 256 bytes (a page) of data to be programmedat previously erased (FFh) memory locations. A Write Enable instruction must beexecuted before the device will accept the Page Program Instruction (StatusRegister bit WEL= 1). The instruction is initiated by driving the /CS pin lowthen shifting the instruction code “02h” followed by a 24-bit address (A23-A0)and at least one data byte, into the DI pin. The /CS pin must be held low forthe entire length of the instruction while data is being sent to the device.The Page Program instruction sequence is shown in figure 14. If an entire 256byte page is to be programmed, the last address byte (the 8 least significantaddress bits) should be set to 0. If the last address byte is not zero, and thenumber of clocks exceed the remaining page length, the addressing will wrap tothe beginning of the page. In some cases, less than 256 bytes (a partial page)can be programmed without having any effect on other bytes within the samepage. One condition to perform a partial page program is that the number ofclocks can not exceed the remaining page length. If more than 256 bytes aresent to the device the addressing will wrap to the beginning of the page andoverwrite previously sent data. As with the write and erase instructions, the/CS pin must be driven high after the eighth bit of the last byte has beenlatched. If this is not done the Page Program instruction will not be executed.After /CS is driven high, the self-timed Page Program instruction will commencefor a time duration of tpp (See AC Characteristics). While the Page Programcycle is in progress, the Read Status Register instruction may still beaccessed for checking the status of the BUSY bit. The BUSY bit is a 1 duringthe Page Program cycle and becomes a 0 when the cycle is finished and thedevice is ready to accept other instructions again. After the Page Programcycle has finished the Write Enable Latch (WEL) bit in the Status Register iscleared to 0. The Page Program instruction will not be executed if theaddressed page is protected by the Block Protect (BP2, BP1, and BP0) bits. 页程序指令（Page Program）允许从一个字节到256字节（一个页面）之间的数据来写入之前擦除（FFh）的内存位置。 Write Enable 指令必 须先执行，否则设备才会接受Page程序指令（状态寄存器位WEL=1）。指令启动由驱动/Cs线低，然后输入代码“02h” followed by 24位地址 （A23-A0）和至少一个数据字节，在DI线中。Cs线必须在整个instruction期间保持低，直到数据被发送到设备。页程序指令序列见图14。 如果要写入一个完整的256字节页面，则最后一位地址字节（最小有效地址位）应该设置为0。如果最后一位地址字节不是零，且时钟数超过剩 余页面长度，则地址会环回到页面开始。有时可以不影响同页面其他字节而写入部分页面，不需要任何效果的条件是时钟数不能超过剩余页面 长度。如果发送给设备的字节数大于256，则地址会环回到页面开始并覆盖之前发送的数据。 与写入和擦除指令一样，Cs线必须驱动高后八位节字节被读入后。否则Page程序指令不会执行。驱动Cs高后，自动时间的页程序指令将 commence在一个时间段tpp（见AC特性）。在页程序循环进行时，Read Status Register指令可以继续访问以检查BUSY位的状态。 BUSY位是1期 间，并且在完成循环并设备准备接受其他指令后变为0。完成页程序循环后，Write Enable Latch（WEL）位在状态寄存器中清除到0。页程序指 令不会被执行如果.addressed page被保护由Block Protect（BP2、BP1和BP0）位。 10.2.15 Quad Input Page Program (32h) The Quad Page Program instruction allows upto 256 bytes of data to be programmed at previously erased (FFh) memory locations using fourpins: IO0, IO1, IO2, and IO3. The QuadPage Program can improve performance for PROM Programmer andapplications that have slow clock speeds <5MHz. Systems with faster clock speed will notrealize much benefit for the Quad Page Program instruction since the inherent page program time ismuch greater than the time it take to clock-in the data. To use Quad Page Program the Quad Enable inStatus Register-2 must be set (QE=1). A Write Enable instruction must be executed before thedevice will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction isinitiated by driving the /CS pin low then shifting the instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data byte,into the IO pins. The /CS pin must be held low for the entire lengthof the instruction while data is being sent to the device. All other functions of Quad Page Program areidentical to standard Page Program. The Quad Page Program instruction sequence is shown infigure 15. 四位页程序指令（Quad Page Program）允许在4个线上（IO0、IO1、IO2和IO3）使用，能够写入256字节的数据到之前擦除（FFh）的内存位置 。 Quad Page Program可以提高PROM Programmer和具有较慢时钟频率 (<5MHz) 的应用的性能。系统具有更快时钟速度并不会得到Quad Page Program指令的重大benefit，因为其固有的页程序时间大于数据 clock-in所需的时间。要使用Quad Page Program，Quad Enable位（QE）在 状态寄存器-2必须设置（QE=1）。 Write Enable指令必须先执行，否则设备才会接受Quad PageProgram指令（状态寄存器-1，WEL=1）。指令 启动时，将驱动/Cs线低，然后输入代码“32h” followed by 24位地址（A23-A0）和至少一个数据字节，进入IO线。Cs线必须在整个 instruction期间保持低，直到数据被发送到设备。所有其他Quad Page Program的功能与标准页程序相同。 Quad PageProgram指令序列见图 15。 10.2.16 Sector Erase (20h) The Sector Eraseinstruction sets all memory within a specified sector (4K-bytes) to the erasedstate of all 1s (FFh). A Write Enable instruction must be executed before thedevice will accept the Sector Erase Instruction (Status Register bit WEL mustequal 1). The instruction is initiated by driving the /CS pin low and shiftingthe instruction code “20h” followed a 24-bit sector address (A23-A0) (seeFigure 2). The Sector Erase instruction sequence is shown in figure 16. The /CSpin must be driven high after the eighth bit of the last byte has been latched.If this is not done the Sector Erase instruction will not be executed. After/CS is driven high, the self-timed Sector Erase instruction will commence for atime duration of tSE (See AC Characteristics). While the Sector Erase cycle isin progress, the Read Status Register instruction may still be accessed forchecking the status of the BUSY bit. The BUSY bit is a 1 during the SectorErase cycle and becomes a 0 when the cycle is finished and the device is readyto accept other instructions again. After the Sector Erase cycle has finishedthe Write Enable Latch (WEL) bit in the Status Register is cleared to 0. TheSector Erase instruction will not be executed if the addressed page isprotected by the Block Protect (TB, BP2, BP1, and BP0) bits (see StatusRegister Memory Protection table). _sector erase指令（SectorErase）将在指定的部门（4K字节）内设置所有内存为被擦除状态中的所有1（FFh）。 Write Enable指令必须先 执行，否则设备才会接受_sector erase指令（状态寄存器位WEL必须等于1）。指令启动时，将驱动/Cs线低，然后输入代码“20h” followed a 24位部门地址（A23-A0）（见图2）。 Sector Erase指令序列见图16。 Cs线必须在整个instruction期间保持低，直到数据被发送 到设备。所有其他Sector Erase指令的功能与标准 Sector erase相同。 注意：该文段主要是描述sector erase指令的使用方式和流程，不涉及技术细节或硬件特性。 Sector Erase的执行时间（tSE）见AC特性表。 Sector Erase过程进行时，Read Status Register指令可以继续访问以检查BUSY位的状态。 BUSY位是1期间，并且在完成Sector erase循环后变为0。完成Sector erase循环后的Write Enable Latch（WEL）位在状态寄存器中清除为0。 Sector Erase指令不会被执行如果被保护的页面由Block Protect（TB、BP2、BP1和BP0）位保护（见状态寄存器内存保护表）。 10.2.17 32KB Block Erase (52h) The BlockErase instruction sets all memory within a specified block (32K-bytes) to theerased state of all 1s (FFh). A Write Enable instruction must be executedbefore the device will accept the Block Erase Instruction (Status Register bitWEL must equal 1). The instruction is initiated by driving the /CS pin low andshifting the instruction code “52h” followed a 24-bit block address (A23-A0)(see Figure 2). The Block Erase instruction sequence is shown in figure 17. The/CS pin must be driven high after the eighth bit of the last byte has beenlatched. If this is not done the Block Erase instruction will not be executed.After /CS is driven high, the self-timed Block Erase instruction will commencefor a time duration of tBE1 (See AC Characteristics). While the Block Erasecycle is in progress, the Read Status Register instruction may still beaccessed for checking the status of the BUSY bit. The BUSY bit is a 1 duringthe Block Erase cycle and becomes a 0 when the cycle is finished and the deviceis ready to accept other instructions again. After the Block Erase cycle hasfinished the Write Enable Latch (WEL) bit in the Status Register is cleared to0. The Block Erase instruction will not be executed if the addressed page isprotected by the Block Protect (TB, BP2, BP1, and BP0) bits (see StatusRegister Memory Protection table) 块擦除指令（Block Erase）将在指定的块（32K字节）内设置所有内存为被擦除状态中的所有1（FFh）。 Write Enable指令必须先执行，否则 设备才会接受块擦除指令（状态寄存器位WEL必须等于1）。指令启动时，将驱动/Cs线低，然后输入代码“52h” followed a 24位块地址（ A23-A0）（见图2）。块擦除指令序列见图17。 Cs线必须在整个instruction期间保持低，直到数据被发送到设备。所有其他块擦除指令的功能与标准块擦除相同。 注意：该文段主要是描述块擦除指令的使用方式和流程，不涉及技术细节或硬件特性。 块擦除的执行时间（tBE1）见AC特性表。块擦除过程进行时，Read Status Register指令可以继续访问以检查BUSY位的状态。 BUSY位是1期间 ，并且在完成块擦除循环后变为0。完成块擦除循环后的Write Enable Latch（WEL）位在状态寄存器中清除为0。 块擦除指令不会被执行如果 被保护的页面由Block Protect（TB、BP2、BP1和BP0）位保护（见状态寄存器内存保护表）。 For W25Q16, user should not issue 32KBBlock Erase (52h) instruction to the top or bottom 32KB block when SEC bit inStatus Register is set to “1”. 对于W25Q16设备，用户不应该在SEC位（状态寄存器）中设置为“1”时发送32KB块擦除指令（52h）到顶部或底部的32KB块中。 这意味着，当SEC位为“1”时，单个块擦除指令（20h）的执行是安全的，而不是块擦除指令（52h） 10.2.18 64KB Block Erase (D8h) The BlockErase instruction sets all memory within a specified block (64K-bytes) to theerased state of all 1s (FFh). A Write Enable instruction must be executedbefore the device will accept the Block Erase Instruction (Status Register bitWEL must equal 1). The instruction is initiated by driving the /CS pin low andshifting the instruction code “D8h” followed a 24-bit block address (A23-A0)(see Figure 2). The Block Erase instruction sequence is shown in figure 18. The/CS pin must be driven high after the eighth bit of the last byte has beenlatched. If this is not done the Block Erase instruction will not be executed.After /CS is driven high, the self-timed Block Erase instruction will commencefor a time duration of tBE (See AC Characteristics). While the Block Erasecycle is in progress, the Read Status Register instruction may still beaccessed for checking the status of the BUSY bit. The BUSY bit is a 1 duringthe Block Erase cycle and becomes a 0 when the cycle is finished and the deviceis ready to accept other instructions again. After the Block Erase cycle hasfinished the Write Enable Latch (WEL) bit in the Status Register is cleared to0. The Block Erase instruction will not be executed if the addressed page is protectedby the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register MemoryProtection table) 块擦除指令（Block Erase）将在指定的块（64K字节）内设置所有内存为被擦除状态中的所有1（FFh）。 Write Enable指令必须先执行，否则 设备才会接受块擦除指令（状态寄存器位WEL必须等于1）。指令启动时，将驱动/Cs线低，然后输入代码“D8h” followed a 24位块地址（ A23-A0）（见图2）。块擦除指令序列见图18。 Cs线必须在整个instruction期间保持低，直到数据被发送到设备。所有其他块擦除指令的功能与标准块擦除相同。 注意：该文段主要是描述块擦除指令的使用方式和流程，不涉及技术细节或硬件特性。 块擦除的执行时间（tBE）见AC特性表。块擦除过程进行时，Read Status Register指令可以继续访问以检查BUSY位的状态。 BUSY位是1期间， 并且在完成块擦除循环后变为0。完成块擦除循环后的Write Enable Latch（WEL）位在状态寄存器中清除为0。 块擦除指令不会被执行如果被 保护的页面由Block Protect（TB、BP2、BP1和BP0）位保护（见状态寄存器内存保护表） NEOT For W25Q16, user should not issue 64KBBlock Erase (D8h) instruction to the top or bottom 64KB block when SEC bit inStatus Register is set to “1”. 对于W25Q16设备，用户不应该在SEC位（状态寄存器）中设置为“1”时发送64KB块擦除指令（D8h）到顶部或底部的64KB块中。 这意味着，当SEC位为“1”时，单个块擦除指令（20h）的执行是安全的，而不是块erase指令（D8h） 10.2.19 Chip Erase (C7h / 60h) The ChipErase instruction sets all memory within the device to the erased state of all1s (FFh). A Write Enable instruction must be executed before the device willaccept the Chip Erase Instruction (Status Register bit WEL must equal 1). Theinstruction is initiated by driving the /CS pin low and shifting theinstruction code “C7h” or “60h”. The Chip Erase instruction sequence is shownin figure 19. The /CS pin must be driven high after the eighth bit has beenlatched. If this is not done the Chip Erase instruction will not be executed.After /CS is driven high, the self-timed Chip Erase instruction will commencefor a time duration of tCE (See AC Characteristics). While the Chip Erase cycleis in progress, the Read Status Register instruction may still be accessed tocheck the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erasecycle and becomes a 0 when finished and the device is ready to accept otherinstructions again. After the Chip Erase cycle has finished the Write EnableLatch (WEL) bit in the Status Register is cleared to 0. The Chip Eraseinstruction will not be executed if any page is protected by the Block Protect(BP2, BP1, and BP0) bits (see Status Register Memory Protection table) 芯片擦除指令（Chip Erase）将所有设备内存设置为被擦除状态中的所有1（FFh）。 Write Enable指令必须先执行，否则设备才会接受芯片擦 除指令（状态寄存器位WEL必须等于1）。指令启动时，将驱动/Cs线低，然后输入代码“C7h”或“60h”。芯片擦除指令序列见图19。 Cs线必须在整个instruction期间保持低，直到数据被发送到设备。所有其他芯片擦除指令的功能与标准芯片擦除相同。 注意：该文段主要是描述芯片erase指令的使用方式和流程，不涉及技术细节或硬件特性。 芯片擦除的执行时间（tCE）见AC特性表。芯片擦除过程进行时，Read Status Register指令可以继续访问以检查BUSY位的状态。 BUSY位是1期 间，并且在完成芯片擦除循环后变为0。完成芯片erase循环后的Write Enable Latch（WEL）位在状态寄存器中清除为0。 芯片erase指令不会 被执行如果任何页面被Block Protect（BP2、BP1和BP0）位保护（见状态寄存器内存保护表） 10.2.20 Erase Suspend (75h) The EraseSuspend instruction “75h”, allows the system to interrupt a sector or blockerase operation and then read from or program data to, any other sector orblock. The Write Status Register instruction (01h) and Erase instructions (20h,52h, D8, C7h, 60h ) are not allowed during suspend. Erase Suspend is valid onlyduring the sector or block erase operation. If written during the chip erase orprogram operation, the Erase Suspend instruction is ignored. A maximum of time of“tsus” (See AC Characteristics) is required to suspend the erase operation. TheBUSY bit in the Status register will clear to 0 after Erase Suspend. 停用擦除指令（Erase Suspend）“75h”允许系统中断_sector或块擦除操作，然后读取或写入任何其他_sector或块。 Write_status寄存器指 令(01h)和擦除指令(20h、52h、D8、C7h、60h )在暂停期间不允许。 停用擦除仅在sector或块擦除操作有效。 如果写入在chip erase或程序 操作中，则停用擦除指令无效。 需要“tsus”（见AC特性）最大时间范围来suspend擦除操作。 Status寄存器中的Busy位在EraseSuspend后 清零 10.2.21 Erase Resume (7Ah) The Erase Resumeinstruction must be written to resume the sector or block erase operation afteran Erase Suspend. After issued the BUSY bit in the status register will be setto a 1 and the sector or block will complete the erase operation. Resumeinstructions will be ignored unless an Erase Suspend operation is active. 停用擦除指令后，resume指令必须写入来恢复_sector或块擦除操作。发出后，Status寄存器中的Busy位将设置为1，并开始完成erase操作。Resume指令除非active的EraseSuspend操作外，就会被忽略 10.2.22 Power-down (B9h) Although thestandby current during normal operation is relatively low, standby current canbe further reduced with the Power-down instruction. The lower power consumptionmakes the Power-down instruction especially useful for battery poweredapplications (See ICC1 and ICC2 in AC Characteristics). The instruction isinitiated by driving the /CS pin low and shifting the instruction code “B9h” asshown in figure 22. The /CS pin must be driven high after the eighth bit hasbeen latched. If this is not done the Power down instruction will not beexecuted. After /CS is driven high, the power-down state will entered withinthe time duration of tDP (See AC Characteristics). While in the power-downstate only the Release from Power-down / Device ID instruction, which restoresthe device to normal operation, will be recognized. All other instructions areignored. This includes the Read Status Register instruction, which is alwaysavailable during normal operation. Ignoring all but one instruction makes thePower Down state a useful condition for securing maximum write protection. Thedevice always powers-up in the normal operation with the standby current ofICC1. 尽管在正常运行时的电压消耗相对较低，但Power-down指令可以进一步降低 Standby Current。这种更低的功耗特性使得Power-down指令尤其 适合于电池驱动的应用（见AC特性中的ICC1和ICC2）。 指令启动时，将驱动/Cs线低，然后输入代码“B9h”（见图22）。 Cs线必须在 Eighth bit被锁定后驱动高。如果不这样做，则Power-down指令不会被执行。驱动 Cs线高后，设备进入power down状态的时间范 围为tDP（见AC特性）。在power down状态下，只有Release from Power-down /Device ID指令（该指令恢复设备到正常运行状态）会被识别 。 所有其他指令都会忽略。包括 Read Status Register指令，这始终在正常运行状态下可用。忽略所有但一个指令，使得Power Down状态成为最 大写保护的有用条件。设备始终在正常运行状态下启动，采用ICC1的 standby电压 10.2.23 High Performance Mode (A3h) TheHigh Performance Mode (HPM) instruction must be executed prior to Dual or QuadI/O instructions when operating at high frequencies (see FR and FR1 in ACElectrical Characteristics). This instruction allows pre-charging of internalcharge pumps so the voltages required for accessing the Flash memory array arereadily available. The instruction sequence includes the A3h instruction codefollowed by three dummy byte clocks shown in Fig. 23. (Contact Winbond for thelatest 25Q data sheet with updated HPM diagram). After the HPM instruction isexecuted, the device will maintain a slightly higher standby current (Icc3)than standard SPI operation. The Release from Power-down or HPM instruction(ABh) can be used to return to standard SPI standby current (Icc1). 高性能模式（High Performance Mode，HPM）指令必须在执行双端或四端输入（Dual或Quad I/O）指令之前，当运行频率较高时（见AC电气特 性中的FR和FR1）。 这个指令允许内置电压泵的预充电，使得访问Flash memory数组所需的电压 readily可用。 指令序列包括A3h指令代码后 接着三位dummy字节钟表（详见Winbond最新的25Q数据sheet更新的HPM图表）。 执行HPM指令后，设备会维持比标准SPI运作中的 standby电流略高（Icc3）。 释放Power-down或HPM指令（ABh）可以返回到标准SPI standby电流（Icc1） 10.2.24 Release Power-down or HighPerformance Mode / Device ID (ABh) The Release from Power-down or Highperformance Mode / Device ID instruction is a multi-purpose instruction. It canbe used to release the device from the power-down state or High PerformanceMode, or obtain the devices electronic identification (ID) number. To releasethe device from the power-down state or High Performance Mode, the instructionis issued by driving the /CS pin low, shifting the instruction code “ABh” anddriving /CS high as shown in figure 24. Release from power-down will take thetime duration of tRES1 (See AC Characteristics) before the device will resumenormal operation and other instructions are accepted. The /CS pin must remainhigh during the tRES1 time duration. When used only to obtain the Device IDwhile not in the power-down state, the instruction is initiated by driving the/CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes.The Device ID bits are then shifted out on the falling edge of CLK with mostsignificant bit (MSB) first as shown in figure 25. The Device ID values for theW25Q80, W25Q16, and W25Q32 are listed in Manufacturer and Device Identificationtable. The Device ID can be read continuously. The instruction is completed bydriving /CS high. When used to release the device from thepower-down state and obtain the Device ID, the instruction is the same aspreviously described, and shown in figure 25, except that after /CS is drivenhigh it must remain high for a time duration of tRES2 (See AC Characteristics).After this time duration the device will resume normal operation and otherinstructions will be accepted. If the Release from Power-down / Device IDinstruction is issued while an Erase, Program or Write cycle is in process(when BUSY equals 1) the instruction is ignored and will not have any effectson the current cycle 释放Power-down或高性能模式/设备ID指令是一种多用性指令。它可以用于释放设备从Power-down状态或高_performance模式，或获得设备的电子身份（ID）号。 要释放设备从Power-down状态或高性能模式，指令是通过驱动/Cs线低，输入代码“ABh”，并驱动Cs线高（见图24）。 释放Power-down将在 tRES1（见AC特性）的时间范围内完成，设备才能恢复正常运作和接受其他指令。 Cs线必须在tRES1时间范围内保持高位。 当仅用于获得Device ID，而不处于Power-down状态时，指令是通过驱动/Cs线低，输入代码“ABh”后接着3个dummy字节。 Then设备ID的位移 将出现在CLK下降边缘的最主要位（MSB）前面（见图25）。 W25Q80、W25Q16和W25Q32等设备ID值列在制造商和设备识别表中。设备ID可以连续 读取。指令完成时是通过驱动Cs线高 当使用指令释放设备从Power-down状态并获取设备ID时，这个指令与之前描述的一致，除非在 Cs线高后必须保持高位的时间范围为tRES2（见 AC特性）。在此时间范围内，设备恢复正常运作并接受其他指令。 当Release from Power-down / Device ID指令发起时，如果正在进行Erase、Program或Write循环（Busy位等于1）则该指令会被忽略，并不会 对当前循环产生任何影响 10.2.25 Read Manufacturer / Device ID (90h)The Read Manufacturer/Device ID instruction is an alternative to the Releasefrom Power-down / Device ID instruction that provides both the JEDEC assignedmanufacturer ID and the specific device ID. The Read Manufacturer/Device IDinstruction is very similar to the Release from Power-down / Device IDinstruction. The instruction is initiated by driving the /CS pin low andshifting the instruction code “90h” followed by a 24-bit address (A23-A0) of000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device IDare shifted out on the falling edge of CLK with most significant bit (MSB)first as shown in figure 26. The Device ID values for the W25Q80, W25Q16, andW25Q32 are listed in Manufacturer and Device Identification table. If the24-bit address is initially set to 000001h the Device ID will be read first andthen followed by the Manufacturer ID. The Manufacturer and Device IDs can beread continuously, alternating from one to the other. The instruction iscompleted by driving /CS high. 读取制造商/设备ID指令（Read Manufacturer/Device ID）是一个替代Releasefrom Power-down / Device ID指令，提供 JEDEC指定的制造商ID和特定的设备ID。 readManufacturer/Device ID指令与Release from Power-down / Device ID指令非常相似。指令是通过驱动/Cs线低，输入代码“90h”后接 着24位地址（A23-A0）的000000h之后。然后，Winbond制造商的EFh和设备ID将在CLK下降边缘的最主要位（MSB）前面传出，如图26所示。 W25Q80、W25Q16和W25Q32等设备ID值列在制造商和设备识别表中。如果24位地址最初设置为000001h，则设备ID首先被读取，然后是制造商ID。 制造商和设备ID可以连续读取，交替从一个到另一个。指令完成时是通过驱动Cs线高 10.2.26 Read Unique ID Number(1) The ReadUnique ID Number instruction accesses a factory-set read-only 64-bit numberthat is unique to each W25Q80, W25Q16 or W25Q64 device. The ID number can beused in conjunction with user software methods to help prevent copying orcloning of a system. The Read Unique ID instruction is initiated by driving the/CS pin low and shifting the instruction code “4Bh” followed by a four bytes ofdummy clocks. After which, the 64-bit ID is shifted out on the falling edge ofCLK as shown in figure 27. 读取唯一ID号指令（ReadUnique ID Number）访问每个W25Q80、W25Q16或W25Q64设备的工厂设置的.read-only。 64位ID号可以与用户软件方 法结合起来，以帮助预防系统复制或克隆。 Read Unique ID指令是通过驱动/Cs线低，输入代码“4Bh”后接着四个字节dummy clock之后，再 在CLK下降边缘传出64位ID，如图27所示。这个ID号可以用来和用户软件结合起来，以帮助防止系统复制或克隆。 10.2.27 JEDEC ID (9Fh) For compatibilityreasons, the W25Q80/16/32 provides several instructions to electronicallydetermine the identity of the device. The Read JEDEC ID instruction iscompatible with the JEDEC standard for SPI compatible serial memories that wasadopted in 2003. The instruction is initiated by driving the /CS pin low andshifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID bytefor Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity(ID7-ID0) are then shifted out on the falling edge of CLK with most significantbit (MSB) first as shown in figure 28. For memory type and capacity valuesrefer to Manufacturer and Device Identification table. 为了兼容性原因，W25Q80/16/32提供了多个指令来电子确定设备的身份。 Read JEDEC ID指令是兼容JEDEC标准（SPI兼容序列记忆的标准）， 于2003年广泛采用。指令是通过驱动/Cs线低，然后输入代码“9Fh”之后，EFh制造商ID字节和两个Device ID字节，Memory Type (ID15-ID8)和Capacity (ID7-ID0)，在CLK下降边缘传出最主要位（MSB）第一，如图28所示。对于记忆类型和存储容量值参考制造商和设备识别表 10.2.28 Mode Bit Reset (FFh or FFFFh) ForFast Read Dual/Quad I/O operations, Mode Bits (M7-0) are implemented to furtherreduce instruction overhead. By setting the Mode Bits (M7-0) to “Ax” hex, thenext Fast Read Dual/Quad I/O operation does not require the BBh/EBh instructioncode (See 10.2.12 Fast Read Dual I/O and 10.2.13 Fast Read Quad I/O for detaildescriptions). If the system controller is Reset during operation it willlikely send a standard SPI instruction, such as Read ID (9Fh) or Fast Read (0Bh),to the 25Q16/32/80. However, as with most SPI Serial Flash memories, the25Q80/16/32 does not have a hardware Reset pin, so if Mode bits are set to “Ax”hex, the 25Q80/16/32 will not recognize any standard SPI instructions. Toaddress this possibility, it is recommended to issue a Mode Bit Resetinstruction as the first instruction after a system Reset. Doing so willrelease the Mode Bits for the “Ax” hex state and allow Standard SPIinstructions to be recognized. The Mode Bits Reset instruction is shown infigure 29. 为了减少快速读取双/四端输入操作的指令负担，模式位（M7-0）实现了进一步的优化。通过设置模式位（M7-0）为“Ax”字节hex，下一次快 速读取双/四端输入操作不需要使用BBh/EBh指令代码（见10.2.12 Fast Read Dual I/O和10.2.13 Fast ReadQuad I/O的详细描述）。 如果系统控制器在运行时Reset，那么它很可能会发送一个标准SPI指令，例如Read ID（9Fh）或快速读取（0Bh），到25Q16/32/80。然而，与 大多数SPI序列flash记忆相似，25Q80/16/32没有硬件Reset信号，因此如果模式位设为“Ax”hex，那么25Q80/16/32不会认识任何标准SPI指令 。为了解决这一问题，建议在系统Reset后发送一个模式位Reset指令作为第一个指令。这样可以释放模式位的“Ax”hex状态，并允许标准 SPI指令被识别。模式位Reset指令如图29所示 To reset Mode Bit during Quad I/Ooperation, only eight clocks are needed. The instruction is “FFh”. To resetMode Bit during Dual I/O operation, sixteen clocks are needed to shift ininstruction “FFFFh” 要在四端输入操作中恢复模式位，仅需要8t个时钟。指令为“FFh”。 在双端输入操作中，恢复模式位需要16个时钟来传入指令“FFFFh”。
| 
[复制链接]
狗仔卡
发表于 2025-9-16 16:36:13
支持！
反对！
收藏
分享
帖子提升卡
置顶卡
沉默卡
喧嚣卡
变色卡
千斤顶
