- »ý·Ö
- 248
- ÏÂÔØ·Ö
- ·Ö
- ÍþÍû
- µã
- Ô´´±Ò
- µã
- ÏÂÔØ
- ´Î
- ÉÏ´«
- ´Î
- ×¢²áʱ¼ä
- 2007-2-17
- ¾«»ª
|
24#
·¢±íÓÚ 2007-6-17 20:10:28
|
Ö»¿´¸Ã×÷Õß
À´×Ô£º ËÄ´¨µÂÑô À´×Ô ËÄ´¨µÂÑô
DDR2 Ò²Óи´Î»ÐźÅѽ£¬¾ÍÊÇ¿´²»¶®ËµÃ÷£¬ÀÏÕÅÄܲ»ÄܺÃÈË×öµ½µ×°ïæ·ÒëÒ»ÏÂѽ£¿
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z.
ÁíÍâÕâ¸öÐźÅÊÇNBÀ´µÄ»¹ÊÇSBÀ´µÄ£¿ |
|