ÇóASUS P5RD2 -VM Ö÷°åµÄµãλͼ

»áÔ±1078

P5RD2-VM°åCPUÒ»¹©µçÉϹܺÍ3110»µ,»»ºóÓÐÒìÏì,ÓÃADP3168´úÔ­À´µÄADP3181ÄÜÏÔʾÁË,µ«ÌáʾCPU¹©µç¹ýѹ,°´F1ºó½øÈëϵͳ,ÈÏÓ²¼þºó,ÖØÆô¶¯¾Í²»ÔÙÏÔʾÁË,²âCPU¹©µçûÓÐÊä³ö.ADP3168µÚ11½ÅÓÐÆô¶¯µçѹ,¹©µç¹ÜG¼«Îª11V,ÉϹÜG¼«µçѹ0V

»áÔ±400730

60-MBB3W5-A12.rar (112.38 KB, ÏÂÔØ´ÎÊý: 43)

2011-4-20 22:07 ÉÏ´«

µã»÷ÎļþÃûÏÂÔظ½¼þ

»áÔ±1078

лл,ÎҵİåºÅÊÇ:60-MBB3W0-B15

»áÔ±1078

ADP3168Ó¦¸ÃÄÜ´úADP3181°É?´Ó×ÊÁÏÉÏ¿´Ö÷Òª¾ÍÊǵÚ6½ÅÓÐÇø±ðÁË.
ADP3168:
1 to 6  VID4 to VID0, VID5 :Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing
                                           a Logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation
                                           voltage from 0.8375 V to 1.6 V. Leaving VID4 through VID0 open results in the ADP3168 going into
                                           a no CPU mode, shutting off its PWM outputs.

ADP3181:
1 to 5  VID4 to VID0 : Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a Logic 1
                                     if left open. When in normal operation mode, the DAC output programs the FB regulation voltage based
                                     on the condition of the CPUID pin (see Table 4 and Table 5). Leaving VID4 through VID0 open results in
                                      ADP3181 going into a no CPU mode, shutting off its PWM outputs.
6  CPUID:                    CPU DAC Code Selection Input. When this pin is pulled > 4.25 V, the internal DAC reads its inputs based
                                     on the VRM 9 VID table (see Table 4). When this pin is <4 V, the DAC reads its inputs based on the VRD
                                      10 VID table (see Table 5) and treats CPUID as the VID5 input. (ADP3181JRQ, VRD10 only)

»***

ÔÚÏß´ò¿ªµÄÎļþÎÞ·¨´«ËÍ°¦£¡