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标题: arm开关中断汇编接口 [打印本页]

作者: バ幸福De右岸 时间: 2016-7-26 07:24
标题: arm开关中断汇编接口

;                                              EQUATES
;********************************************************************************************************
CPU_ARM_CTRL_INT_DIS  EQU    0xC0                         ; Disable both FIQ & IRQ

;********************************************************************************************************
;                                     CODE GENERATION DIRECTIVES
;********************************************************************************************************
AREA _CPU_A_CODE_, CODE, READONLY
ARM

;$PAGE
;********************************************************************************************************
;                                     CRITICAL SECTION FUNCTIONS
;
; Description : Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking, the
;             state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
;             are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
;             The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
;
; Prototypes  : CPU_SR  CPU_SR_Save (void);
;             void CPU_SR_Restore(CPU_SR cpu_sr);
;********************************************************************************************************
CPU_SR_Save
      MRS    R0, CPSR
CPU_SR_Save_Loop
                                                            ; Set IRQ & FIQ bits in CPSR to DISABLE all interrupts
      ORR    R1, R0, #CPU_ARM_CTRL_INT_DIS
      MSR    CPSR_c, R1
      MRS    R1, CPSR                                     ; Confirm that CPSR contains the proper interrupt disable flags
      AND    R1, R1, #CPU_ARM_CTRL_INT_DIS
      CMP    R1,    #CPU_ARM_CTRL_INT_DIS
      BNE    CPU_SR_Save_Loop                               ; NOT properly DISABLED (try again)
      BX    LR                                           ; DISABLED, return the original CPSR contents in R0

CPU_SR_Restore                                                 ; See Note #2
      MSR    CPSR_c, R0
      BX    LR

;$PAGE
;********************************************************************************************************
;                                  CPU ASSEMBLY PORT FILE END
;********************************************************************************************************
      END

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