求ASUS P5RD2 -VM 主板的点位图 - 迅维网

2011-4-20 22:07 上传

点击文件名下载附件

: 登录/注册后看高清大图

947.49 KB, 下载次数: 2, 下载积分: 下载分 -2 分, 下载 1 次

作者: 马任知 时间: 2011-4-20 22:31
谢谢,我的板号是:60-MBB3W0-B15

作者: 马任知 时间: 2011-4-20 22:56
ADP3168应该能代ADP3181吧?从资料上看主要就是第6脚有区别了.
ADP3168:
1 to 6  VID4 to VID0, VID5 :Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing
                                       a Logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation
                                       voltage from 0.8375 V to 1.6 V. Leaving VID4 through VID0 open results in the ADP3168 going into
                                       a no CPU mode, shutting off its PWM outputs.

ADP3181:
1 to 5  VID4 to VID0 : Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a Logic 1
                                 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage based
                                 on the condition of the CPUID pin (see Table 4 and Table 5). Leaving VID4 through VID0 open results in
                                    ADP3181 going into a no CPU mode, shutting off its PWM outputs.
6  CPUID:                   CPU DAC Code Selection Input. When this pin is pulled > 4.25 V, the internal DAC reads its inputs based
                                 on the VRM 9 VID table (see Table 4). When this pin is <4 V, the DAC reads its inputs based on the VRD
                                    10 VID table (see Table 5) and treats CPUID as the VID5 input. (ADP3181JRQ, VRD10 only)

: 登录/注册后看高清大图

: 登录/注册后看高清大图

作者: 会员398335 时间: 2011-4-21 10:30
在线打开的文件无法传送唉！

欢迎光临迅维网 (https://www.chinafix.com/)