[ 本帖最后由 卫青 于 2007-12-16 10:17 编辑 ]作者: 尹谷丰 时间: 2007-12-11 00:16
我再加2个问题
1但是SLP_S3#始终低电平 IO怎么会让ATX上电呢?
2说是ATX PG到I/O的PG 信号贯孔不通,到底IO得不到PG还是南桥得不到PG 而影响正常上电?作者: 尹谷丰 时间: 2007-12-11 00:22
2说是ATX PG到I/O的PG 信号贯孔不通,到底IO得不到PG还是南桥得不到PG 而影响正常上电?
卫青你有条件
能不能拿块好板把IO到南桥的PG搞断 看看是什么故障
另外问一下SMSC的IO后面的型号是哪种 我们以后遇到这个IO也注意南桥的PG是IO给的作者: 小鱼学维修 时间: 2007-12-11 08:46
按理说PG信号没到IO,南桥也就没有收到PG信号,主板应该无复位才对.引起反复断通断电倒是没遇到过!作者: 心在飞翔 时间: 2007-12-11 09:00
PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid.
PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached
their nominal values. PWROK must not glitch, even if RSMRST# is low.
1. SYSRESET# is recommended for implementing the system reset button. This saves
external logic that is needed if the PWROK input is used. Additionally, it allows for
better handling of the SMBus and processor resets, and avoids improperly
reporting power failures.
2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
are less than one RTC clock period may not be detected by the ICH9.
3. In the case of true PWROK failure, PWROK will go low before VRMPWRGD.
4. When PWROK goes inactive, a host power cycle reset will occur. A host power cycle
is the assertion of SLP_S3#, SLP_S4#, and SLP_S5#, and the deassertion of these
signals 3-5 seconds later. The Management Engine remains powered throughout
this cycle.作者: 恨天无眼 时间: 2007-12-11 19:40
这下都没得看了。英文。。作者: 张先生 时间: 2007-12-12 09:46
我把管理员的英文答复翻译一下,有理解错误的地方请大家指正。