作者: 梧桐叶 时间: 2010-5-31 13:56
1 片选 当cpu选中他就会拉低 2spi的接受发送叫主入从出 你就理解成数据交换的线吧 有不规则的波形 3 写保护 4 8 不用解释了吧 5 和2相对的主入从出 6 时钟作者: 张先生 时间: 2010-5-31 14:00
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
SI Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device.
VDD Power Supply To provide power supply (3.0-3.6V).
VSS Ground
